
GCC 4.9 :

IA-32/x86-64

    -mfpmath=sse is now implied by -ffast-math on all targets where SSE2 is supported.
    Intel AVX-512 support was added to GCC. That includes inline assembly support, new registers and extending existing ones, new intrinsics (covered by corresponding testsuite), and basic autovectorization. AVX-512 instructions are available via the following GCC switches: AVX-512 foundation instructions: -mavx512f, AVX-512 prefetch instructions: -mavx512pf, AVX-512 exponential and reciprocal instructions: -mavx512er, AVX-512 conflict detection instructions: -mavx512cd.
    It is now possible to call x86 intrinsics from select functions in a file that are tagged with the corresponding target attribute without having to compile the entire file with the -mxxx option. This improves the usability of x86 intrinsics and is particularly useful when doing Function Multiversioning.
    GCC now supports the new Intel microarchitecture named Silvermont through -march=silvermont.
    GCC now supports the new Intel microarchitecture named Broadwell through -march=broadwell.
    Optimizing for other Intel microarchitectures have been renamed to -march=nehalem, westmere, sandybridge, ivybridge, haswell, bonnell.
    -march=generic has been retuned for better support of Intel core and AMD Bulldozer architectures. Performance of AMD K7, K8, Intel Pentium-M, and Pentium4 based CPUs is no longer considered important for generic.
    -mtune=intel can now be used to generate code running well on the most current Intel processors, which are Haswell and Silvermont for GCC 4.9.
    Support to encode 32-bit assembly instructions in 16-bit format is now available through the -m16 command-line option.
    Better inlining of memcpy and memset that is aware of value ranges and produces shorter alignment prologues.
    -mno-accumulate-outgoing-args is now honored when unwind information is output. Argument accumulation is also now turned off for portions of programs optimized for size.
    Support for new AMD family 15h processors (Excavator core) is now available through the -march=bdver4 and -mtune=bdver4 options.

GCC 5 :
IA-32/x86-64

    New ISA extensions support AVX-512{BW,DQ,VL,IFMA,VBMI} of Intel's CPU codenamed Skylake Server was added to GCC. That includes inline assembly support, new intrinsics, and basic autovectorization. These new AVX-512 extensions are available via the following GCC switches: AVX-512 Vector Length EVEX feature: -mavx512vl, AVX-512 Byte and Word instructions: -mavx512bw, AVX-512 Dword and Qword instructions: -mavx512dq, AVX-512 FMA-52 instructions: -mavx512ifma and for AVX-512 Vector Bit Manipulation Instructions: -mavx512vbmi.
    New ISA extensions support Intel MPX was added to GCC. This new extension is available via the -mmpx compiler switch. Intel MPX is a set of processor features which, with compiler, run-time library and OS support, brings increased robustness to software by run-time checking pointer references against their bounds. In GCC Intel MPX is supported by Pointer Bounds Checker and libmpx run-time libraries.
    The new -mrecord-mcount option for -pg generates a Linux kernel style table of pointers to mcount or __fentry__ calls at the beginning of functions. The new -mnop-mcount option in addition also generates nops in place of the __fentry__ or mcount call, so that a call per function can be later patched in. This can be used for low overhead tracing or hot code patching.
    The new -malign-data option controls how GCC aligns variables. -malign-data=compat uses increased alignment compatible with GCC 4.8 and earlier, -malign-data=abi uses alignment as specified by the psABI, and -malign-data=cacheline uses increased alignment to match the cache line size. -malign-data=compat is the default.
    The new -mskip-rax-setup option skips setting up the RAX register when SSE is disabled and there are no variable arguments passed in vector registers. This can be used to optimize the Linux kernel.





